The devices under test are p-channel LTPS-TFTs with a top-gate structure. Firstly, the amorphous silicon thin film was shaped into a polysilicon thin film by the ELA process. Then, the poly-Si layer was patterned into active islands by use of wet etch, followed by a 50-nm-thick SiO₂ deposition using the LPCVD. The low-temperature oxide (LTO) was used as the gate dielectric. Subsequently, a 300-nm-thick Al was sputtered and patterned into gate electrodes. Boron at a dose of 4 × 10¹⁵ cm² was implanted into the source and drain by self-aligned technology. Before defining the contact holes, a passivation layer was formed by the LPCVD depositing 500-nm SiO₂. The 700-nm thick Al-1% Si was used as the metal leads. Finally, the devices were sintered in a synthesis gas at 420 °C for 30 min. In this experiment, the device channel width and length are and respectively, and the measured unit area gate oxide capacitance (C_ox) is about 6.91 × 10⁻⁸ F/cm².

In this work, the transfer characteristics were measured by using Agilent B1500, and the low frequency noise values were measured using Keysight E4727A.^[18,19]

The transfer characteristics of poly-Si TFTs are shown in Fig. 1, which were measured at V_DS=−0.1 V. The extracted threshold voltage (V_th) was measured to be about -8.79 V using the linear extrapolation method. The field effect mobility ( ) was about . Moreover, the extracted sub-threshold swing (SS) was −0.34 V/decade, which was defined as the reciprocal of the slope of the log (I_DS)–V_GS curve in the sub-threshold region.

Fig. 1.

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	Fig. 1. Transfer characteristics of poly-Si TFT.

Figure 2 shows the measured transfer characteristics of poly-Si TFTs under NBS when V_GS is −37 V, which shows that the threshold voltage continuously shifts with the stress time increasing, and the sub-threshold slope also slightly increases. By using the linear extrapolation method, V_TH was extracted from −8.32 V to −11.02 V after the negative bias stress had been applied for 5000 s.

Fig. 2.

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	Fig. 2. Transfer characteristics of poly-Si TFT measured under different stress times.

Four different bias stress experiments were carried out with the same stress time, and the values of negative bias stress voltage (V_GS) were −25 V, −29 V, −33 V, and −37 V, respectively. Figure 3 shows a linear relationship between and stress time in the log-log coordinate system, which indicates that the degradation behaviors have a strong correlation with the stress time and stress voltage. It is consistent with previous investigations in Refs. [12,20], and [21]. Like NBS degradation of MOSFETs, the shift of V_TH can be modeled as^[14,20] 1 where t is the stress time, n is the time exponent, E_a is the activation energy, (t_ox is the gate oxide thickness), and a is the acceleration distance of electron ( Å).^[22] As shown in Fig. 3, follows a power-law dependence on the stress time. The time exponent varies from 0.26 to 0.32 with the increasing of bias voltage, which is extracted from the slope of the fitted line. The results were consistent with previous reports about bulk MOSFETs^[12] and poly-Si TFT,^[21] where the typical value of n is between 1/4 and 1/3.^[23]

Fig. 3.

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	Fig. 3. Log–log plot of versus stress time in poly-Si TFTs with different bias stress voltages.

Meanwhile, the normalized decreases and SS increases with stress time increasing as shown in Fig. 4, which is attributable to the carrier trap in the gate oxide and the generation of interface states near the Si/SiO₂ interface.^[24] The result indicates that more interface states may be induced in the channel, which leads the sub-threshold swing to increase.

Fig. 4.

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	Fig. 4. Variations of normalized hole field effect mobility and normalized sub-threshold swing in the poly-Si TFTs when stress voltage is −37 V.

The relationship between the SS and the interface state density (D_it) can be expressed as^[25] 2 where ( is about 0.35 eV in this work).

Besides, as the stress time increases, the interface state traps cause the average free time of carriers to decrease and further to result in the decline of carrier field effect mobility. The variation of the field effect mobility can be calculated from^[25] 3 where is the hole field effect mobility before stress and η is a fitting parameter. According to Eq. (3), the variation of interface states has a considerable influence on carrier mobility.

According to the above description about the device fabrication process, the low-temperature oxide (LTO) was used as the gate dielectric of DUT, which may be sensitive to moisture exposure. As reported in Ref. [26], molecular H₂O may sink into the gate oxide layer at an opportune state, which may be induced SiOH groups as expressed by the simplified equation^[13] 4 In this paper, an assumption was made that a lot of SiOH groups are induced in the gate oxide or near the channel interface. Under the negative bias stress, carriers leaped over the surface barrier, and then broke the Si–OH bonds with disassociation energy of above 1.2 eV, resulting in the generation of Si* and negative charge OH⁻. The Si* groups formed into interface states, and the partial OH⁻ groups were captured by oxide traps, thus forming into the fixed negative charges in the gate oxide layer. A negative charge generation model is presented to expound the process^[11] as shown in Fig. 5.

Fig. 5.

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	Fig. 5. Schematic illustration of negative charge generation model in poly-Si TFT.

In addition, as previously reported,^[11,27] the impact ionization phenomenon is more accessibly induced under higher negative bias stress, which further resulted in localized states in the gate oxide or near the channel interface. Therefore, the degradation behaviors becomes more evident as the gate voltage increases as shown in Figs. 2–4.

As reported in Refs. [8–15] in the NBS degradation of poly-TFTs, the shift of the threshold voltage may be affected by both fixed charges in gate oxide and interface states, and it can be expressed as^[28,29] 5 and 6 According to Eq. (5), the contributions of stress-induced charges OH ( ) and interface states ( ) to can be divided. Based on Eq. (6), the and can be calculated, and the results are plotted in Fig. 6. The results indicate that stress-induced interface states have more contributions to the threshold voltage shift than the stress-induced oxide trapped charges. It is determined that the variations of are dominated by the stress-induced Si* groups in the Si/SiO₂ interface.

Fig. 6.

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	Fig. 6. Plots of separation of stress-induced oxide trapped charges and interface states versus time.

The variations of N_it and N_oxt are presented in Fig. 7, under different stress voltages. is the difference between and , which increases with stress increasing voltage. It further shows that N_it dominates the degradation of poly-Si TFTs more at a higher stress voltage.

Fig. 7.

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	Fig. 7. Variations of trap density versus stress voltage ( ).

As reported in Refs. [30–32] several theories can be used to explain the origin of 1/f noise: the carrier number fluctuation ( ) model, the mobility fluctuation ( ) model and carrier number with correlated mobility fluctuation ( – ) model. As proposed by Ghibaudo et al.,^[32] in the – model the variation of mobility induced by the fluctuation of interfacial charges is considered. Therefore, it provides a general description of LFN in various actual cases.

The above models have considered the noise related to carrier number fluctuations due to the trapping process in oxide traps. As reported by Dimitriadis^[33] and Wang,^[34] the measured noise under higher drain current intensity can be well described by the use of – model. However, the measured excess noise under low drain current intensity may be dominated by the trapping process in the grain boundary.^[33,34] Therefore, it should be modeled by considering the grain boundary effect.^[34]

As reported in Refs. [8–15], the variation of grain boundary trap is less related to NBS effect. In order to simplify the following calculations, the classical – model is used in this paper.

To further investigate the low frequency noise in these poly-Si TFTs, the curves of drain current power spectral densities versus the drain current are plotted in Fig. 8. According to the classical – model, the normalized drain current spectral density ( can be given by^[33,35–37] 7 where is the fitting parameter which may be related to the Coulomb scattering, g_m is the transconductance, and S_Vfb is the flat band voltage spectral density. Due to uniformly distributed traps in the oxide, S_Vfb can be expressed by^[33,38] 8 where N_t is the trap state density near the Si/SiO2 interface (in units , which includes oxide traps, interface states and border traps, and λ is the tunnel attenuation distance (about 0.1 nm in DUT). Based on Eq. (7), S_Vfb can be extracted from Fig. 8. Furthermore, based on Eq. (8), the normalized N_t is plotted in Fig. 9. Those increases further reveal that more localized states and trapped charges are induced after NBS.

Fig. 8.

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	Fig. 8. Curves of normalized noise versus drain current power spectral density before and after NBS (VDS = −0.5 V).

Fig. 9.

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	Fig. 9. Normalized Nt (defined as ) versus negative gate bias voltage.

Note that here in Eq. (7) the effect of the grain boundary trap on the low frequency noise is not taken into consideration. Therefore, the excess noise observed in the low drain current of poly-Si TFT cannot be well described by using Eq. (7).^[33,34] In addition, the grain boundary trap related degradation phenomenon cannot be evaluated by using Eq. (7).^[33,34] More accurate noise models should be adopted, which were proposed by Dimitriadis^[33] and Wang.^[34] The trapping and de-trapping of carriers tunneling from the inversion layer to the oxide traps near the interface cause 1/f noise. Therefore, based on the charge tunneling principle, the tunneling distance is affected by the time constant ( ).^[36] In order to have a qualitative spatial distribution of traps in the gate oxide, the relationship between frequency and tunneling distance can be expressed as follows:^[36,38] 9 where (about 10⁻¹⁰ s) is the time constant, x is the tunneling distance, is the tunneling attenuation coefficient (about 10⁸ cm⁻¹). The plot of calculated density of trapped charges versus depth before and after stress experiment are graphed in Fig. 10, those results are in agreement with the previous discussion about the variations of the transfer characteristics.

Fig. 10.

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	Fig. 10. Spatial distribution of oxide trapped charge density in gate oxide before and after stress.